1. Field of the Invention
The present invention relates to a display device and a method for driving the display device, and more specifically a display device using a light-emitting element and having a memory control circuit. The memory control circuit controls writing into and reading from a memory such as a SRAM (Static Random Access Memory).
2. Related Art
A display device where a light-emitting element is disposed in each pixel and which displays an image by controlling emission of the light-emitting element is described hereinafter.
In this specification, the light-emitting element means an element (EL element) having a structure in which an organic compound layer that emits light when an electric field is generated is sandwiched between an anode and a cathode, but the light-emitting element is not limited thereto.
Further, in this specification, the light-emitting element means both an element that utilizes light emitted when making a transition from a singlet exciton to a ground state (fluorescence) and an element that utilizes light emitted when making a transition from a triplet exciton to a ground state (phosphorescence).
An organic compound layer includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, or the like. The light-emitting element is given as a laminated structure of an anode, a light-emitting layer, and a cathode in this order. The basic structure can be modified into a laminate of an anode, a hole injection layer, a light-emitting layer, an electron injection layer, and a cathode in this order, or a laminate of an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and a cathode in this order.
A display device comprises a display and a peripheral circuit for inputting signals to the display.
A structure of the display is shown in a block diagram of FIG. 8.
In FIG. 8, a display 2000 comprises a source signal driver circuit 2107 comprising a shift register 2110, a LAT A 2111 and a LAT B 2112, a gate signal driver circuit 2108 and a pixel portion 2109. A display controller 2002 which inputs data into the source signal driver circuit 2107 and the gate signal driver circuit 2108 is provided. The pixel portion has pixels disposed in a matrix configuration. In addition, a signal control circuit 2001 comprises a memory controller 2003, a CPU 2004, memories A 2005 and B 2006.
Thin film transistors (hereinafter, referred to as TFTs) are arranged in each pixel. Here, a method for arranging two TFTs in each pixel and controlling light emitted from the light-emitting element of each pixel is described.
FIG. 9 shows a structure of a pixel portion of a display device.
Source signal lines S1 to Sx, gate signal lines G1 to Gy, and electric power source supply lines V1 to Vx are arranged in a pixel portion 2700, and x columns and y rows (where x and y are natural numbers) of pixels are also arranged in the pixel portion. Each pixel 2705 has a switching TFT 2701, a driver TFT 2702, a storage capacitor 2703, and a light-emitting element 2704.
The pixel comprises one source signal line S of the source signal lines S1 to Sx, one gate signal line G of the gate signal lines G1 to Gy, one electric power source supply line V of the electric power source supply lines V1 to Vx, the switching TFT 2701, the driver TFT 2702, the storage capacitor 2703, and the light-emitting element 2704.
A gate electrode of the switching TFT 2701 is connected to the gate signal line G, and either a source region or a drain region of the switching TFT 2701 is connected to the source signal line S, while the other is connected to a gate electrode of the driver TFT 2702 or to one electrode of the storage capacitor 2703. Either a source region or a drain region of the driver TFT 2702 is connected to the electric power source supply line V, while the other is connected to an anode or a cathode of the light-emitting element 2704. One of two electrodes of the storage capacitor 2703, namely an electrode that is not connected to the driver TFT 2702 and the switching TFT 2701, is connected to the electric power source supply line V.
In this specification, the anode of the light-emitting element 2704 is referred to as a pixel electrode, and the cathode of the light-emitting element 2704 is referred to as an opposing electrode in the case where the source region or the drain region of the driver TFT 2702 is connected to the anode of the light-emitting element 2704. On the other hand, the cathode of the light-emitting element 2704 is referred to as a pixel electrode, and the anode of the light-emitting element 2704 is referred to as an opposing electrode in the case where the source region or the drain region of the driver TFT 2702 is connected to the cathode of the light-emitting element 2704.
Further, an electric potential imparted to the electric power source supply line V is referred to as an electric power source electric potential, and an electric potential imparted to the opposing electrode is referred to as an opposing electric potential.
The switching TFT 2701 and the driver TFT 2702 may be either p-channel TFTs or n-channel TFTs. However, it is preferable that the driver TFT 2702 is a p-channel TFT and the switching TFT 2701 is an n-channel TFT in the case where the pixel electrode of the light-emitting element 2704 is the anode. Meanwhile, it is preferable that the driver TFT 2702 is an n-channel TFT and the switching TFT 2701 is a p-channel TFT in the case where the pixel electrode is the cathode.
Operations in displaying an image in the aforementioned pixel structure are described hereinafter.
Signals are input to the gate signal line G, and an electric potential of the gate electrode of the switching TFT 2701 changes, and then a gate voltage changes. In this way, the signals are input to the gate electrode of the driver TFT 2702 from the source signal line S through a source and a drain of the switching TFT 2701 that is made conductive. Further, the signals are stored in the storage capacitor 2703. The gate voltage of the driver TFT 2702 changes in accordance with the signals input to the gate electrode of the driver TFT 2702, and then the source and the drain are electrically connected. The electric potential of the electric power source supply line V is imparted to the pixel electrode of the light-emitting element 2704 through the driver TFT 2702. The light-emitting element 2704 thus emits light.
A method for expressing gray scale with pixels having such a structure is described. Methods for expressing gray scale can be roughly divided into an analog method and a digital method. The digital method has advantage of being resistant to fluctuation on TFTs as compared with the analog method. A digital gray scale expression method is focused upon here. A time gray scale method can be given as the digital gray scale expression method. The time gray scale driving method is described in detail hereinafter.
The time gray scale driving method is a method for expressing gray scale by controlling a period during which each pixel of a display device emits light. When a period for displaying one image is taken as one frame period, one frame period is divided into a plurality of sub frame periods.
Lighting or non-lighting, namely whether the light-emitting element of each pixel is made to emit light or not to emit light every sub frame period, controls the period during which the light-emitting element emits light in one frame period, and gray scale of each pixel is expressed.
The method for driving the time gray scale method is described in detail with reference to timing charts of FIGS. 10A and 10B. Note that FIGS. 10A and 10B show an example of expressing gray scale using 4-bit digital image signals. Note also that FIG. 9 may be referred to regarding the structure of the pixels. Here, in accordance with an external electric power source (not shown), the opposing electric potential can be switched to have an electric potential on the order of the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential) or to have enough electric potential difference to make the light-emitting element 2704 emit light between the opposing electric potential and the electric power source supply lines V1 to Vx.
One frame period F is divided into a plurality of sub frame periods SF1 to SF4. The gate signal line G1 is selected first in the first sub frame period SF1, and digital image signals are input from the source signal lines S1 to Sx to each of the pixels having the switching TFTs 2701 with the gate electrode connected to the gate signal line G1. The driver TFT 2702 of each pixel is to be in an ON state or an OFF state by the input digital image signals.
The term “ON state” for a TFT in this specification indicates that the source and the drain are in a conductive state in accordance with the gate voltage. Further, the term “OFF state” for a TFT indicates that the source and the drain are in a non-conductive state in accordance with the gate voltage.
At this point, the opposing electric potential of the light-emitting element 2704 is set nearly equal to the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential); therefore, the light-emitting element 2704 does not emit light even in a pixel where the driver TFT 2702 is in an ON state. The aforementioned operations are repeated for all of the gate signal lines G1 to Gy, and a writing period Tal is completed. Note that a writing period of the first sub frame period SF1 is referred to as Tal. In general, a writing period of the j-th sub frame period (where j is a natural number) is referred to as Taj.
The opposing electric potential changes to have enough electric potential difference to make the light-emitting element 2704 emit light with the electric power source electric potential, when the writing period Tal is completed. A display period Ts1 thus begins. Note that a display period of the first sub frame period SF1 is referred to as Ts1. In general, a display period of the j-th sub frame period (where j is a natural number) is referred to as Tsj. The light-emitting element 2704 of each pixel is to be in a light-emitting state or a non-light-emitting state according to the input signals during the display period Ts1.
The aforementioned operations are repeated for all of the sub frame periods SF1 to SF4, and then one frame period Fl is completed. Here, lengths of the display periods Ts1 to Ts4 in the sub frame periods SF1 to SF4 are set appropriately, and gray scale is expressed by an accumulating total of the display periods in the sub frame period during which the light-emitting element 2704 emit light in one frame period F. In other words, gray scale is expressed with a total amount of lighting time within one frame period.
A method for generally expressing 2n gray scale by inputting n-bit digital video signals is described. At this point, one frame period is divided into n sub frame periods SF1 to SFn, for example, and the ratio of lengths of the display periods Ts1 to Tsn in the sub frame periods SF1 to SFn are set so as to be Ts1: Ts2: . . . : Tsn-1: Tsn=20:2−1: . . . :2−n+2: 2−n+1. Note that the lengths of the writing periods Tal to Tan are all the same.
Gray scale of a pixel in one frame period is determined by figuring out a total of the display period Ts during which a light-emitting state is selected of the light-emitting element 2704 for the duration of the one frame period. For example, when brightness in the case where a pixel emits light over a whole display period is taken to be one hundred percent at the time of n=8, one percent of brightness can be expressed when the pixel emits light in Ts7 and Ts8. Sixty percent of brightness can be expressed in the case of selecting Ts 6, Ts 4, and Ts 1.
A circuit for converting signals into signals for time gray scale is required in order to display with such a time gray scale method described above. FIG. 2 shows a schematic diagram of a conventional control circuit. A control circuit 200 comprises memories A 201 and B 202 for storing data, a logic circuit for reading data and writing the data into the memory (W-LOGIC 203), and a logic circuit for reading the date from the memory and outputting the data to a display 205 (R-LOGIC 204).
FIG. 3 shows a timing chart of the conventional control circuit. Data is written and read alternately using the memories A 201 and B 202 in order to allow digital data that is input to the W-LOGIC 203 to be adapted to the time gray scale method.
When the R-LOGIC 204 reads signals stored in the memory A 201, digital video signals that can be used for the next frame period are simultaneously input to the memory B 202 through the W-LOGIC 203 and starts to be stored.
Thus, the control circuit 200 has the memories A 201 and B 202 that can store digital video signals of 1 frame period each, and samples the digital video signals by using the memories A 201 and B 202 alternately.
Conventionally, the control circuit is put in a stand-by state (Wait) until the next reading signal is given after writing into the memory A 201 or B 202. Further, roles of the memories A201 and B202 is switched from/to writing to/from reading in timing with reading which takes more time. (FIG. 3)
In a conventional method, a reading time is set much longer than a writing time. Therefore, there is no problem with a method in which writing is performed as needed and operating functions are switched after reading is completed.
However, there is a problem with a driving method that has little difference between reading time of a memory and writing time of a memory. The timing of writing into a memory is delayed according to the conventional method in which there is a Wait state until reading is performed after writing. As a result, the conventional method has a problem that a frame frequency decreases.